The present invention relates in general to data processing devises employing metal oxide semiconductor technology, and in particular, to the degradation of device performance from hot carrier injection into the gate oxide layer of the metal oxide semiconductor transistors.
Integrated circuit devices, such as microprocessors, using metal oxide semiconductor transistor technology experience a performance degradation over time due to the injection of hot carriers into the gate insulating oxide layer. As a consequence of the hot carrier injection, the threshold voltage of the MOS transistors increases, with a concomitant decrease in speed of the devices, at a given operating voltage. Typically, a lifetime of the semiconductor device is specified such that over the specified lifetime, the device will operate within the manufacturers specifications for speed and operating voltage. Note that a set of device specifications may trade off performance against other considerations, for example, the device specifications may provide for an increased clock speed at a higher operating voltage (with a quadratic increase in power consumption as a result) or alternatively may provide for reduced speed performance in association with a reduced operating voltage with a concomitant reduction in power consumption.
As performance specifications are increased, the hot carrier injection problem is exacerbated. At higher speeds and associated operating voltages, the injection of hot carriers into the oxide layer increases. Typically, to ensure that an integrated circuit device will operate within the specified voltage and temperature ranges, and at the specified operating frequency over the lifetime of the device, manufacturers characterize the degradation due to HCI using worst case conditions. This results in an excessive safety margin, and generally leads to a clock frequency specification that constrains the specified operating speed of the device significantly below the underlying capabilities of the integrated circuit. Consequently, with an increasing demand for devices with faster speeds, particularly with respect to microprocessors, the need has arisen for improved methods of characterizing HCI induced performance degradation at the chip level.
Chip level degradation may be evaluated using automatic test equipment (ATE) to run a set of patterns repeatedly, and then characterize the degradation of the device over time. However, the ATE is an expensive resource, and the availability of the ATE is limited by demands imposed on ATE facilities by production testing requirements. Additionally, performance degradation evaluation in an ATE environment implicates a large number of static patterns, which must be loaded into the ATE memory, if the device under test (DUT) is to be adequately stressed. Supplying sufficient memory in the ATE may also represent a substantial expense. Consequently, there is a need in the art for apparatus and methods to perform chip level evaluation of HCI performance degradation. The methods and apparatus should alleviate the limitations of the present techniques imposed by cost and time constraints.
The aforementioned needs are addressed by the present invention. Accordingly, there is provided, in a first form, a method of evaluating data processing devices. The method includes setting a first preselected stress condition on the device. One or more stress cycles are executed on the device. Executing the one or more stress cycles includes executing a first predetermined set of instructions on the device. A first preselected value of a performance parameter of the device, is set on the device and is it determined if the device fails for the first value of the performance parameter.
There is also provided, in a second form, a data processing system. The system includes circuitry operable for setting a first preselected stress condition on the device. One or more stress cycles are executed on the device. The step of executing the one or more stress cycles includes executing a first predetermined set of instructions on the device, by circuitry in the system. Also included is circuitry operable for setting a first preselected value of a performance parameter of the device, and circuitry operable for determining if the device fails for the first value of the performance parameter.
Additionally, there is provided, in a third form, a computer program product embodied in a tangible storage medium, the program product for evaluating data processing devices. The program product includes a program of instructions for setting a first preselected stress condition on the device, and executing one or more stress cycles on the device. Executing the one or more stress cycles includes executing a first predetermined set of instructions on the device. Instructions are also included for setting a first preselected value of a performance parameter of the device. Further instructions determine if the device fails for the first value of the performance parameter.
The foregoing has outlined rather broadly the features and technical advantages of the present invention in order that the detailed description of the invention that follows may be better understood. Additional features and advantages of the invention will be described hereinafter which form the subject of the claims of the invention.